1. Field of the Invention
The present invention is directed in general to the field of electronic circuits. In one aspect, the present invention relates to a data latch apparatus and system for transferring data in a datapath and methods for operating same.
2. Description of the Related Art
In electronic circuits and data processing systems, flip-flops are commonly used in digital circuits for propagating data through various datapaths. Such flip-flops typically consist of master and slave latches, each of which uses its own clock for receiving data inputs and propagating data within the circuit/system. For example, the master latch captures input data during assertion of the capture clock, while the slave latch launches data during assertion of the launch clock. Testability typically requires the flip-flop to have an additional circuit portion that allows multiple flip-flops to be connected into a serial scan register chain for loading and unloading test vectors to distinguish between functional and test modes. Proper operation during either functional or test modes requires that the input data be stable for a predetermined time commonly known as the “hold time” of the flip-flop. In modern systems, hold violations are most pervasive in datapaths that have minimal logic between pairs of flip-flops. It is generally accepted that serial scan register chains are susceptible to hold violations because there is minimal logic between pairs of flip-flops that are serially coupled to each other.
Level-sensitive scan design (LSSD) includes an additional test clock input that is used for capturing data into the master latch. Hence, an LSSD flip-flop can be considered to have three clocking inputs: A clock, B clock, and C clock. The master latch has at least one data port for receiving functional data when its LSSD C clock is active, and also has at least one data port for receiving scan data when its LSSD A clock is active. In addition, the slave latch has at least one data port for receiving data from the master latch when the LSSD B clock is active. During test operations, the two latches form a master/slave pair with one scan input, one scan output, and non-overlapping scan clocks A and B which are held low during functional operation, but which cause the scan data to be latched when pulsed high during scan operation. The LSSD A clock can be independently controlled relative to the LSSD B clock, and their non-overlap can be designed such that hold violations are not a problem in test mode. However, a disadvantage with LSSD flip-flops is that the B and C clocks are both high-speed clocks which toggle during functional mode. In addition to the increased system complexity of providing two high-speed clocks, the LSSD approach also requires higher clocking power in functional mode.
To reduce the number of clock signals required, single clocked multiplexed data flip-flop (Mux-D FF) designs have been proposed for use with scan/test designs so that only a single clock is used for functional and scan modes. Referring to FIG. 1, an example Mux-D FF design is shown in which a storage cell 140 has only one clock 131 input to its L1 master latch 110 and L2 slave latch 120. FIG. 2 is a timing diagram of the clock signals for implementing the Mux-D FF shown in FIG. 1, with CLOCKB 202 representing an inverted version of the input CLOCK 201 which is applied as the input clock signal 131 to the inverter 130 to generate the CLOCKB signal. In this way, CLOCKB is provided as the clock signal 132 to the master latch 110 and CLOCK is provided as the clock signal 131 to the slave latch 120. The inverted input clock (CLOCKB) 132 is received at the L1 master latch 110 which also receives the data input 111 from a multiplexer 100 which selects between D functional data 101 and I scan data 102 based on the scan enable (SE) selection signal 103. The output of the Mux-D FF storage cell 140 appears at Q output line 123 from the L2 slave latch 120. While the Mux-D FF uses only a single input clock 131 for the storage cells 110, 120, data cannot be flushed through the scan path 102, 111, 121, 123 (for system reset or manufacturing test). In addition, the data path delay (both functional data path 101, 111, 121, 123 and scan path 102, 111, 121, 123) must be long enough to avoid timing problems due to clock skew which results from the difference in arrival time of the clock signal 131 at different latches or flops 110, 120. Such clock skew is difficult to control due to the nature of the clock tree distribution and design with existing chip system designs, and as a result, a clock skew with value of 150 ps is not uncommon. Such clock skew is significant and can result in hold time violations during scan mode. To address hold time violations, buffers or delay elements have conventionally been inserted between the out and scan-in port of the next flip-flop, but this additional circuitry increases the circuit area size and consumes additional power.
Accordingly, a need exists for an improved data latch, system and method of operations that addresses various problems in the art that have been discovered by the above-named inventors where various limitations and disadvantages of conventional solutions and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow, though it should be understood that this description of the related art section is not intended to serve as an admission that the described subject matter is prior art.